第1 章 FPGA 架构总体设计 ········································································· 1
1.1 FPGA 芯片研制流程·········································································· 1
1.2 FPGA 架构设计流程·········································································· 7
1.3 FPGA 规模和资源划分 ····································································· 17
1.4 FPGA 中功能模块划分 ····································································· 20
本章参考文献 ······················································································ 26
第2 章 FPGA 中时钟网络 ·········································································· 30
2.1 简介 ···························································································· 30
2.2 FPGA CDN 建模 ············································································· 33
2.3 时钟网络设计方法 ·········································································· 43
2.4 时钟网络的灵活性 ·········································································· 48
2.5 路由级联 ······················································································ 51
2.6 仿真实验 ······················································································ 55
2.7 时钟网络热学建模 ·········································································· 61
2.8 仿真实验 ······················································································ 62
本章参考文献 ······················································································ 66
第3 章 FPGA 中电源/地线网络和漏电流 ······················································· 68
3.1 电源/地线网络 ··············································································· 68
3.2 IR-DROP 分析与优化 ········································································ 71
3.3 漏电流组成 ··················································································· 73
3.4 降低漏电流的方法 ·········································································· 74
3.5 基于VIA 分布的IR-DROP 分析 ··························································· 77
3.6 仿真实验 ······················································································ 81
3.7 不均匀测试点的IR-DROP 求解 ··························································· 87
3.8 FPGA 电源网络IR-DROP 分析 ···························································· 89
本章参考文献 ······················································································ 94
第4 章 FPGA 中可编程逻辑单元 ································································· 98
4.1 基于多路选择器的逻辑单元 ······························································ 98
4.2 基于四输入LUT 的可编程逻辑单元的设计 ·········································· 102
4.3 LUT 的模型与实现 ········································································ 103
4.4 LUT 的输入数目K 的确定 ······························································· 106
4.5 进位逻辑 ····················································································· 109
4.6 基于查找表结构的FPGA 的不足 ······················································· 115
4.7 AIC 结构逻辑簇 ············································································ 117
4.8 基于AIC 结构FPGA 的逻辑簇 ························································· 120
4.9 面向AIC 的映射工具及结构评估平台 ················································ 124
4.10 结构特征匹配的AIC 簇互连优化 ···················································· 125
4.11 仿真分析和比较 ·········································································· 131
本章参考文献 ····················································································· 133
第5 章 FPGA 中可编程I/O 模块 ································································· 136
5.1 可编程I/O 系统结构 ······································································ 136
5.2 IOE 中的可编程输入缓冲器设计 ······················································· 138
5.3 IOE 中的可编程输出缓冲器设计 ······················································· 144
5.4 可编程I/O 的后端版图设计······························································ 156
5.5 高可靠I/O 模块的后端版图与测试 ····················································· 166
5.6 可编程I/O 的供电策略 ··································································· 172
5.7 全芯片IO 的ESD 技术 ··································································· 173
本章参考文献 ····················································································· 179
第6 章 FPGA 中DDR 存储器接口 ······························································ 182
6.1 DDR SDRAM 芯片的工作原理 ·························································· 182
6.2 FPGA 芯片中DDR 存储器接口系统设计 ············································· 184
6.3 DDR 存储器接口控制器的设计和验证 ················································ 191
6.4 延时锁相技术 ··············································································· 194
6.5 延时锁定环电路的分析与对比 ·························································· 196
6.6 数字延时锁定环电路的性能分析与优化 ·············································· 201
6.7 延时锁定环线性模型与稳定性分析 ···················································· 205
本章参考文献 ····················································································· 209
第7 章 FPGA 中数字延时锁定环 ································································ 213
7.1 实现相移的全数字延迟锁定环 ·························································· 213
7.2 数字控制延时链 ············································································ 215
7.3 时间数字转换器 ············································································ 220
7.4 双向移位计数器 ············································································ 221
7.5 鉴相器与锁定逻辑 ········································································· 222
7.6 延迟锁定环的版图设计 ··································································· 224
7.7 延迟锁定环环路的仿真 ··································································· 224
7.8 芯片的物理实现与测试平台 ····························································· 225
7.9 DDR 接口的数据通路的测试验证 ······················································ 227
7.10 数字延时锁定环的测试 ································································· 229
7.11 数字占空比矫正电路的测试 ···························································· 232
本章参考文献 ····················································································· 234
第8 章 FPGA 中连线连接盒 ······································································ 236
8.1 引言 ··························································································· 236
8.2 问题分析 ····················································································· 237
8.3 利用模拟退火算法优化CB 拓扑结构 ·················································· 241
8.4 实验及结果分析 ············································································ 246
8.5 连线开关盒的电路结构设计方法 ······················································· 251
本章参考文献 ····················································································· 259
第9 章 FPGA 中互连线段长度分布 ····························································· 261
9.1 所提优化方法的基本思路 ································································ 261
9.2 以面积延时积最小为目标的优化 ······················································· 265
9.3 针对所提优化方法的讨论 ································································ 268
9.4 设计实验 ····················································································· 269
9.5 FPGA 芯片的设计实现 ···································································· 270
9.6 芯片的测试准备 ············································································ 272
本章参考文献 ····················································································· 275
第10 章 FPGA 中的配置模块 ···································································· 277
10.1 配置系统的基本组成及特点 ···························································· 277
10.2 配置系统的功能需求 ···································································· 279
10.3 配置系统的硬件结构分析 ······························································ 281
10.4 配置码流协议的结构及其对配置系统的影响 ······································· 286
10.5 配置系统总体框架 ······································································· 292
10.6 配置码流协议的设计 ···································································· 297
10.7 配置系统的电路设计与实现 ···························································· 300
10.8 配置系统采用的验证工具与方法 ······················································ 305
10.9 配置系统的验证方案与功能点的抽取 ················································ 310
10.10 配置系统功能验证平台的设计 ······················································· 312
10.11 配置系统验证结果 ······································································ 319
本章参考文献 ····················································································· 324
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数字滤波器的MATLAB与FPGA实现——Altera/Verilog版作者简介