In-Target System Analyzer for
Actel Core8051™ Microcontroller Core
ISA-ACTEL51专为 ACTEL51 设计，采用FS2公司独有的 On-Chip Instrumentation（芯片级在线调试仪；OCI）和调试器，通过Actel 的FlashPro Lite 实现目标连接，并具有四个硬件执行断点、无限的软件断点，以及可选的触发器和追踪功能。
FS2 产品与Actel 产品的紧密配合，能让使用FS2 之 OCI 工具开发以Actel Core8051 为基础 FPGA 系统的客户，大幅缩短设计周期和降低开发成本。Keil IDE 可与FS2 的工具完美结合。
特点
· 支持 bank switching
· 可读写全部处理器寄存器, SFRs, program memory 和 data memory
· Go, halt processor run control
· 步执行汇编或C 指令
· 无限制软断点设置
· 可下载 binary, Intel Hex或OMF51
· 可达4 硬件执行断点
· 跟踪窗口可以显示汇编、C或混合显示
· 在源码窗口中可设置、软硬件断点
Logic NavigatorTM for Actel FPGAs
Logic Analyzer and Debug Tool for Actel Programmable Logic
专为Actel FPGAs设计。
1、特点：
· 基于FS2 OCI技术跟踪和触发Actel FPGA 的信号分析
· 用户可在Actel ProASIC, ProASIC(PLUS), MX, SX,和AX devices配置任意节点的逻辑分析
· 支持各个级别的触发
· 可存储出发条件
· 图形化用户界面可通过波形或文本输出
· 命令行Tcl/tk 指令接口
· 可配置的跟踪和触发的优化选择
· 通过 Actel FlashPro 或FlashPro Lite 和目标板连接
· OCI 发生器迅速产生配置 OCI 逻辑块选项并且可以产生实例代码。
· 分析达4096个节点
· 可达32个可选的外部触发接口
2、 System Navigator for Nios II
System Navigator Products for Nios II Embedded Processors
专为Nios II设计，采用FS2公司独有的 On-Chip Instrumentation（芯片级在线调试仪；OCI）技术的调试器
特点 Nios II套件 SNAV-NIOS II-USBProbe SNAV-NIOS II-ETHProbe ISA-NIOS II/T Probe
执行断点数 2 4 4 4
数据/周期断点 2 4 4 4
跟踪深度 16 frames Unlimited Unlimited Unlimited (on- chip)
128K frames (off-chip)
数据/总线周期跟踪 No Yes Yes Yes
性能分析 No Yes Yes Yes
跟踪时间标记 No NO NO Yes
主机连接方式 USB 1.1 USB 2.0 USB 2.010/100 Ethernet USB 1.1 / EPP
触发 No NO NO Yes
目标连接方式 JTAG JTAG JTAG Mictor-38
离线跟踪 No NO NO Yes
多核支持 No Yes Yes Yes3、 System Navigator for AMD Alchemy™ Processors
System Navigator tools for
AMD Alchemy Solutions Au1500™ and Au1550™ Processors
支持AMD芯片的独特特点，对AMD Alchemy Au1500™ 和 Au1550™ 处理器深度跟踪调试。扩展调试支持 Windows 和 Linux下的 GDB/Insight调试。低成本下，优秀的源码级调试。同时也支持图形界面下直观方便的Mentor Graphics code|lab和XRAY debuggers 以及Viosoft embedded Linux Arriba 调试。可通过USB或网口与主机通讯。
特点：
利用OCI技术调试
·支持AMD Alchemy Au1500 和 Au1550 处理器和开发板，也支持所有 MIPS 4K™, 4KE™, 4KS™, M4K™, 5K™, 20K™, 24K™, and 25K™ cores
·支持多样的源码级调试环境
·通过SDBBP指令可以无限制设置断点
·单步执行汇编和C代码
·读写全部CPU寄存器
· 无论CPU停止或运行都可读写内存
· MIPS标准的硬件断点(EJTAG version 2.51 or later)
·支持FLASH 编程
·控制CPU运行
·通过JTAG功能底层调试
·单线汇编和反汇编
·支持TCL./TK脚本语言的命令行接口
·包括MDI调试规范的2进制软件接口4、 System Navigator for AMD Geode™ GX and LX Processors
支持处理器：
AMD Geode™ GX 466@0.9W processor
AMD Geode™ GX 500@1.0W processor
AMD Geode™ GX 533@1.1W processor
AMD Geode™ LX 700@0.8W processor
AMD Geode™ LX 800@0.9W processor
AMD Geode™ LX 900@01.5W processor
特点：
·在 Geode GX和Geode LX 处理器利用On-Chip Instrumentation (OCI®) 调试扩展
·读写CPU 寄存器, MSRs, 内存 和I/O
·控制CPU运行
·单步执行汇编指令
·无限的软件断点
·标准的片上跟踪和可选的离片跟踪
·片上跟踪深度达128 x 64-bit帧
·离片跟踪深度达64K x 64-bit 帧 (可选)
·支持系统管理模式,
·单步通过实模式到保护模式过渡直到监控所有的所有寄存器更新
·支持Flash编程
·用调试寄存器执行硬件断点
·可在触发窗口设置复杂触发
·复杂触发可监控地址和周期类型
·单行汇编和反汇编
·跟踪窗口全面执行跟踪
·源码窗口可执行: go; halt; goto cursor; step over/into call
·源码窗口下能够设置和清除软硬件断点
·包括GNU-based GDB 源码级程序调试
· Windows CE Platform Builder 和 在 Windows XP/XPE WinDbg 内核级调试
·支持TCL./TK脚本语言的命令行接口5、System Navigator for Turbo 186 Cores： System Navigator tools for VAutomation Turbo186 Core and
Lantronix DSTni-LX / DSTni-EX Processors
低成本下，优秀的源码级调试工具。可选的图形化界面，直观方便。可通过USB或网口与主机通讯。
特点：
· 控制CPU运行
· 单步执行汇编指令
· 无限的软件断点
· 支持Flash编程
· 用调试寄存器执行硬件断点
· 支持C或汇编语言
· 源码窗口能够显示C语言或混合显示
· 源码窗口可提供运行控制
· 源码窗口能够设置或清除软硬件断点
· 源码窗口允许选择全局或局部变量并增加到变量窗口中
· 触发窗口可设置复杂触发
· 标准TCL./TK脚本语言的命令行接口
System Navigator for MIPS：
System Navigator tools for
MIPS Technologies MIPS32™ and MIPS64™ Cores
提供很多功能例如硬件触发器、跟踪逻辑分析在线仿真。
通过14针EJTAG连接目标板，可通过网口、和usb.或并口连接主机，支持Mdi源码级调试
软件断点
硬件事件识别
Mips芯片包含可配置硬件断点的，可达到15个指令断点执行虚拟地址的识别。
只有当特殊事件被激活，所有的断点都可以禁止被Asid打破的断点。触发事件可以用于跟踪的筛选。
灵活的内外部程序和数据的选择
跟踪可以在片上或片下捕获。内部跟踪深度可以从16到16k字节。当源码只有程序分支被存储
特点
利用OCI技术调试
支持mips芯片
支持基于mips sde 工具链的gun,mentor 图形开发工具和xray以及voisoft
要求ejtag2.5 或以上
标准的片上跟踪和离片跟踪
片上跟踪深度可达1M64BIT字
实时的PC执行跟踪载入、存储地址，和数据跟踪
通过触发器可以切换跟踪状态
Off-chip trace up to 64K 64-bit words
通过SDBBP指令可以无限制设置断点
单步执行汇编和C代码
读写全部CPU和CP0寄存器
支持MIPS标准的硬件断点
支持FLASH 编程
支持多核
控制CPU运行
底层调试通过JTAG功能
单线汇编和反汇编
支持TCL./TK脚本语言的命令行接口
包括MDI调试规范的2进制软件接口
源码级调试直观易用
Eclipse-based Navigator debugger IDE for
MIPS Technologies MIPS32™ and MIPS64™ Cores
与Eclipse兼容的图形化MIPS核开发调试环境8、ABS of the Benefits of MIPS PDtrace™
FS2 System Navigator JTAG ProbesMIPS® Software Toolkit
MIPS® SDE GNU based toolchain, MIPSsim(TM) Instruction Set Simulator,
MIPS® DSP Library and Technical Support
System Navigator for CAST8051
System Navigator tools for
CAST 8051 Synthesizable Microcontroller Cores
支持CPU:
（CAST R8051XC, R80515, R8051, C8051 cores）
兼容开发环境
Keil µVision3 software
12、SNAV-HT80C51
System Navigator tools for Handshake Solutions
HT80C51 and HT80C51MX Clockless Microcontroller Cores
支持CPU: HT80C51 和 HT80C51MX
兼容开发环境：Keil 系列
System Navigator for Mentor M8051EW
System Navigator tools for Mentor M8051EW
Synthesizable Microcontroller Cores
System Navigator for Philips LPC952
System Navigator for
Philips LPC952 Microcontroller
In-Target System Analyzer for Improv Systems Jazz DSP Processor Cores
The ISA-JAZZ In-Target System Analyzer is designed to support the special features and integrated peripherals of the Jazz processor family. It works with the Improv Systems Jazz Standard Tool Suite and provides a JTAG interface to the family DSP processors.
The ISA-Jazz System Analyzer supports JTAG-based debugging for Improv Systems Jazz cores with COOL-Jazz debugging extensions. It features complete run control over one or more Jazz DSP processor cores and enables you to access and modify registers, memory, and I/O. The JTAG based probe works with the Improv Systems tool suite debugger for a graphical user interface. This provides a powerful multi core debug tool for Jazz cores with advanced features at a competitive price.
Key Features
· Read-write all processor registers, memory, and I/O ports
· Go and halt processor run control
· Single step by assembly or C source instruction
· Set hardware and software breakpoints
· Load binary, hex, S-records file formats
· Supports multiple Jazz cores on JTAG chain
· Supports flash programming
· Trigger-in/out signals
· Supported by Jazz debugger and development tool suite
In-Target System Analyzer for LSI Logic ZSP500 DSP Core
The In-Target System Analyzer supports the LSI Logic ZSP™500 synthesizable DSP core. To learn more about the ZSP500 core, visit the web site at www.zsp.comThe ZSP500 core is available with optional FS2 On-chip Instrumentation (OCI®) IP with trace and triggering features for faster system debug and testing. It provides unique performance analysis features that make it easier to find execution bottlenecks and improve performance.
The FS2 system analyzer probe connects to the ZSP500 target system using a 14-pin JTAG connector or 38-pin Mictor cable (with off-chip trace system). The system runs on a Windows®98/NT/2000/XP PC over an IEEE-1284 EPP/bi-directional parallel port.
Key Features
· Supports LSI Logic ZSP500 DSP core
· Features FS2 On-Chip Instrumentation (OCI) technology
· On-chip trace (standard), off-chip trace, or both
· Supports 24-bit addressing
· Real-time PC execution trace
· Load/store address trace
· Detailed Execution Profiling Trace mode for measuring CPU resource utilization
· Point-to-point timing to assist in code performance optimization
· Trace can be gated on/off by on-chip triggers
· Scalable internal trace depth
· External trace port width and speed selectable
· Max trace depth: on-chip 1024 x 64-bit words, off-chip 64K x 64-bit words
· Unlimited software breakpoints
· ZSP hardware breakpoints
· Go, halt processor run control
· Read-write all general registers and control registers
· Supports multiple cores and mixed RISC/DSP development
· Host binary software interface adheres to MDI specification
· Command-line interface window with Tcl scripting
Evaluation and Development Board for Synopsys DesignWare PCI Express IP
The Sitka development and evaluation board was jointly developed by Synopsys and First Silicon Solutions for the Synopsys DesignWare PCI Express IP. The board functions as a standard PCIe add-in card for systems running either the Windows or Linux operating systems.
The Sitka board contains two large Xilinx Virtex-4 FPGA's which allow you to combine your design with the DesignWare PCI Express IP enabling you to test and debug your PCI Express application in hardware. The FPGA's support partitioning of large designs by providing 272 I/O pins between the two FPGA's. These I/O's can be configured for operation up to 1Gpbs point-to-point to provide high throughput data transfers or grouped into sets of unidirectional channels. The FPGA's are configured with on-board ROM that can hold two or more configurations depending on the bitfile compression that is used.
The board enables testing the DesignWare PCI Express IP with multiple PHYs for maximum flexibility in choosing the PHY for the final design. For testing purposes, you can use the built-in FX60 PHY connecting directly to specific connectors like the PCIe interface and SATA drives or through the 360-pin expansion connector. In addition to using the built-in FPGA PHYs, you can use daughter cards connected to the Sitka board via two different connector locations, including the PCI Express Standard PIPE_C (PHY Interface PCI Express Architecture Connector). The Sikta board can run any combination or all of these interfaces simultaneously.
The Sitka board, when used in conjunction with the industry standard DesignWare PCI Express IP enables faster and easier verification of the design in hardware.
Key Features
· PCIe x8 board edge connector (adaptors plug into a PCIe x1 or x4 PC slot)
· PCI Express PHY Interface for PCI Express Architecture Connector (PIPE_C) enables PHY testing through a PHY daughter card
· PMA Interface connector for use with Synopsys PHY daughter cards
· 2 SATA drive connectors
· 2 SFP connector sites for Gigabit Ethernet (GigE)
· 2 XENPAK connector sites for XAUI (adaptors for additional SATA or SFP)
· Cup connectors for TI power source modules
· 2 Xilinx JTAG connectors, one each wired to FX60 and LX100 for using the ChipScope Pro debugger
· Xilinx XC4VFX60-10FF1152
· Xilinx XC4VLX100-10FF1513
· 3 XCF32P configurable FLASH devices for 2 selectable Xilinx image loads
· 2 independent Xilinx-approved clock sources for the Rocket IO (PCIe and SATA)
· 2 clock sources for PMA PHY 'H' connector daughter card
· LEDs for board diagnostics
ISA-QMIPS
ISA-Eclipse
FS2 System Analyzers for
QuickLogic® QuickMIPS™ ESP Family and
Eclipse™ FPGA Devices
ISA-eZ80
In-Target System Analyzer for ZiLOG eZ80 Processor Family
The ISA-eZ80 In-Target System Analyzer is designed to support the special features and integrated peripherals of the eZ80 processor family. It supports the ZiLOG Developer Studio (ZDS) and is integrated with the IAR Embedded Workbench software tools to maximize your productivity.
The system analyzer features complete run control over the eZ80 processor and enables you to access and modify CPU registers, memory, and I/O. FS2's On-Chip Instrumentation (OCI(TM)) debug features built-in to the ZiLOG processors allow FS2 to provide a powerful debug tool with advanced features at a competitive price.
The ISA-eZ80 debugger hardware is contained in a compact chassis that connects to the target system using a 14-pin JTAG connector. The system runs on a Windows® 98/NT/2000 PC over an IEEE-1284 EPP/ECP high-speed parallel port or USB port. The JTAG target interface and high-speed parallel host intface provides typical 8K bytes/sec. loading speeds so you spend more time debugging than waiting for programs to load. A graphical, source level debugger program provides an intuitive, easy to use interface for use with the ZiLOG Developer Studio (ZDS) tools. The system can also be used with the IAR Embedded Workbench debugger interface (sold separately) for complete compatibility with IAR software tools.
IAR Embedded Workbench Interface
IAR Web site
Zilog Web site
Key Features
· Supports ZiLOG eZ80L92, eZ80F91, eZ80F92, eZ80F93, and other processors with available JTAG debug interface
· Read-write all processor registers, memory, and I/O
· Go and halt processor run control
· Trace window with executed assembly and source code
· Single step by assembly or C source instruction
· Unlimited software breakpoints
· Load binary, hex, S-records or COFF (from ZDS) and IAR file formats
· JTAG target and EPP parallel host interface for faster loading
· Flash programming support
· 4 hardware execution breakpoints
· 4 ZDI triggers monitor addrss, address ranges, with option to break on any cycle type
· 4 additional advanced hardware triggers on address, data value, and cycle types, with ranges and masking supported
· Trigger-in/out signals
· Single line assembler and disassembler
· Load code and debug symbols including code, variables, and variable types
· Source level debug from IAR Embedded Workbench interface
· Standalone source debug interface (GUI) supports ZDS tools
FLASH PRO OEM product for Actel ProASIC and ProASICPLUS devices
FPGAView™ Software
Software for Configuring and Debugging Altera and Xilinx FPGA Devices with Tektronix Logic Analyzers
The FPGAView™ software is a PC Windows-based program
FS2 BUS NAVIGATOR™
On-chip FS2 Bus Navigator™ Solutions for AMBA, OCP,
and Sonics SiliconBackplane Bus Systems
The FS2 Bus Navigator™ is used for monitoring signal activity and for debugging complex bus/system interactions in System-on-Chip designs. It allows the user to capture bus activity in real-time and display critical information for analysis on a host PC.
The system consists of an On-chip Instrumentation (OCI®) synthesizable logic block, a JTAG hardware probe, and PC based software for controlling probing and analysis. The OCI passively captures bus activity, buffers it using on-chip RAM, and transfers the collected data off-chip via a JTAG port to the external JTAG probe. The host PC controls the trace collection process and provides captured bus history to the user with an easy-to-use graphical interface. The system runs on a Windows® 2000/XP PC over a USB 2.0 or optional 10/100 Ethernet port. It provides a comprehensive debug tool for complex SoC bus designs at a competitive price.
Key Features
· Captures bus activity in real-time
· Available for AMBA, OCP, and Sonics SiliconBackplane buses
· Captures bus signals and additional user-defined inputs attached to other nodes in the SOC
· Bus clock mode trace stores signals on every clock
· Bus transfer mode aligns bus transfers and response phases for single event triggering using combinations of address, data, and control
· Filtering of wait and idle state cycles in bus transfer mode
· Trace storage qualifiers; single cycle, start or stop trace on any trigger, counter, and state sequencer condition
· Configurable for user defined number of Masters
· Trace buffer stores bus cycles or bus transfers based on RAM memory size
· Up to 16 user defined triggers recognize combinations of 1, 0, X, signal values
· Sequential event monitoring using cascadable trigger states (2 to 16 states)
· Two 32-bit event counter/timers
· Trigger conditions include bus and user defined signals, Event counter/timer value, and Trigger state
· Actions include Trigger, Trace control (start, stop, single), Trig Out control (pulse, assert, negate), Counter control (increment, start, stop, clear), and Goto state
· Trigger position variable in 1/512 increments of trace depth
· User difinable timestamp records duration of each trace frame from the start of trace, displayable as absolute or delta times
· Automatic trace clock frequency measurement allows displaying frame durations in either nanoseconds or clocks
· Multiple external trigger in/out with configurable logic levels
· Easy-to-use graphical software interface with state views and waveform views of data
· Symbolic lookup and signal value naming support for ease of viewing and analysis
· Optional VCD format export for integration with simulation environments
Cadence Emulation Tools Support
Integrating Instrumentation Tools into System-Level Verification Flows. This is a PowerPoint presentation.2100433B
